dd-42900 arinc 429 microprocessor interface device description ddc's dd-42900 provides a complete and flexible interface between a micro- processor and an arinc 429 data bus. the dd-42900 interfaces to a processor through a 128 x 32 bit static ram as well as four 32 x 32 receive fifo's and two 32 x 32 transmit fifo's. the dd-42900 can be easily interfaced to 8- or 16-bit processors via a buffered shared ram configuration. the dd-42900 supports four arinc 429 receive channels (rx0, rx1, rx2 and rx3) each receiving data indepen- dently. the receive data rates (high or low speed) for channel rx0 and rx1 can be programmed independently from rx2 and rx3. the dd-42900 can decode and sort data based on the arinc 429 label and sdi bits via the data match processor and store it in ram and/or fifo's via the data store processor. the dd-42900 supports two arinc 429 transmit channels (tx0 and tx1) and can transmit data independently. the transmit data rate can also be pro- grammed independently. there are two 32 x 32 bit fifo's for each of the trans- mitters that send out data. the dd-42900 has the capability of programming three general purpose interrupts as well as generating an interrupt based on an error condition. the general purpose interrupts can be programmed to trigger other external hardware. they can either be level or pulse triggered. the features built into the dd-42900 enable the user to off-load the host processor and use that processing time to implement operations other than polling the arinc 429 bus. the decoding and sorting of data allows the user to gather data much quicker than past designs. if the user requires a microprocessor in the avionics box, this device will facilitate a clean and quick design. features ? four arinc 429 receive channels 128 x 32 shared ram interface label and destination decoding and sorting two arinc 429 transmit channels two 32 x 32 transmit fifo's interfaces easily to 8- or 16-bit microprocessors built-in fault detection circuitry free ?c? library software available as a chipset: - dd-00429vp asic p - dd-03282gp transceiver - dd-03182vp arinc 429 line driver arinc 429 rx logic arinc 429 rx logic arinc 429 rx logic arinc 429 rx logic arinc 429 tx logic arinc 429 t x logic tx fifo 32 words tx fifo 32 words rx0 fifo 32 words rx1 fifo 32 words rx2 fifo 32 words rx3 fifo 32 words arinc 429 receive 0 arinc 429 receive 1 arinc 429 receive 2 arinc 429 receive 3 arinc 429 transmit 0 arinc 429 transmit 1 2 2 wraparound rx data data match processor data addr ctrl data addr 128 x 16 static ram dmt ram ctrl data addr 128 x 32 static ram rx ram data store processor data addr dmp data addr addr data data interrupt controller 3 16 12 irq data addr control microprocessor or cpu cpu interface data dd-00429fp asic dd-03282 device (2) dd-42900 wraparound wraparound wraparound ? 1995, 1999 data device corporation figure 1. dd-42900 block diagram
2 data device corporation www.ddc-web.com dd-42900 logic inputs/outputs dc supply voltage 4.5 5.5 50 ma device operation @ 16 mhz, typical idd = 30 ma @ 5.0v. dc supply current 0.028 0.032 f dd-42900 built in decoupling. additional external decoupling recommended 0.1 f - 0.01 f. 2.0 vdc iih iil -1.5 -0.2 ma input pins with internal pullup resistor, intel/moto, pol. sel, 8/16 zero wait, master reset vih input logic current low cdd vdc input logic voltage high -350 +350 na idd dc supply decoupling capacitance input logic current high vdd output voltage logic low all other inputs and i/o pins. 0.5 vdc output voltage logic high na +350 -350 vdd-0.5 vdc output leakage current hiz 0.8 vdc note: clk input has hysterisis of 2.0 v max positive going 1.0 v min negative going. vil -500 +500 na input logic voltage low ioz voh vol notes units max min symbol parameter table 2. dd-42900 specifications (tc = +25c unless otherwise specified ) arinc 429 line inputs logic 0 input voltage -6.5 -13.0 vdc nominal -10 v, differential vab vil null input voltage -2.5 +2.5 vdc nominal 0 v, differential vab vnul common mode voltage 5 vdc vcm input impedance to vdd 12 k ohms rh differential input impedance 6 k ohms ri input impedance to ground 12 k ohms rg input capacitance 20 pf ci for all d0 - d15 and dtack, ready and irq outputs input capacitance to vcc 20 pf ch input capacitance to ground 20 pf cg logic 1 input voltage 6.5 13.0 vdc nominal +10 v, differential vab vih table 1. dd-42900 absolute maximum ratings (tc = +25c unless otherwise specified ) parameter min max units dc supply voltage -0.3 7.0 vdc signal input voltage (logic inputs) -0.3 vdd + 0.3 vdc arinc 429 input voltage -29 +29 vdc storage temperature -65 150 c operating temperature -55 125 c lead temperature (soldering) 280 (for 3 sec) c body temperature (soldering) 210 (for 30 sec) c
3 data device corporation www.ddc-web.com dd-42900 arinc 429 receivers the dd-42900 supports four arinc 429 inputs, designated receive channels 0 through 3 (rx0, rx1, rx2 and rx3). the architecture of each of the four receiver circuits is identical and each receives data independently. arinc 429 data is directly received into the dd-42900 with no additional circuitry required. input protection, in accordance with the arinc 429 specifica- tion, is provided along with voltage level translation from +5 v bipolar, nonreturn-to-zero data to conventional, +5 v logic levels.. receive data rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of arinc control register 2. the receiver circuitry will successfully decode an incoming arinc 429 data stream as long as the data rate is within 5% of the nominal rate as determined by the hi speed/low speed bit and the associated arinc clock input (arinc clk 0 or arinc clk 1). the two 1 mhz arinc clock inputs may be tied to the 1 mhz receive clock output or may be connected to another clock source. the arinc clk input should nominally be 10 times (for high-speed mode) or 80 times (for low-speed mode) the desired arinc data rate. arinc clk 0 is used by channels rx0 and rx1 while arinc clk 1 is used by channels rx2 and rx3. filtering and sorting rx data: the receiver circuitry converts the serial data stream to a 32-bit-wide parallel data word. the 32- bit word is processed internally by a data match processor (dmp). it compares the incoming data to a table of data initial- ized by the processor. this determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. the table of data is stored in a 128 word x 16 bit data match table (dmt) ram. when a match between the received arinc 429 data and the criteria stored in a dmt entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the data store processor (dsp). the storage address in the receive ram is the address of the first matching dmt entry minus 200 hex. there are three requirements that must be met in order to match incoming arinc 429 data to each dmt entry: 1) system address label: bits 0-7 of the dmt are compared to the system address label (sal) of the incoming arinc 429 data word. if the dmt sal entry is zero then the sal of the incoming data word is ignored (or considered a match). 2) source/destination bits: bits 8 and 9 of each dmt entry are compared to the source/destination (s/d) bits of the incoming arinc 429 data word. if these bits match, or if bit 10 of the dmt entry is set to a 1, then the s/d bit comparison is considered a match. it is also possible, through the dmp control register 1, to enable ?all call mode? as defined in the arinc 429 specification. when enabled for a particular receive channel, the s/d bits will be considered a match when the incoming arinc 429 data contains a 00 in its s/d bit pair. 3) receive channel number: bits 12 and 13 of each dmt entry are compared to the number of the channel which received the arinc 429 data. a data match has occurred when all of the previous conditions are satisfied; the data will then be stored in a ram location whose address equals the matching dmt entry minus 200 hex. bit 11 of each dmt entry, when set, will cause the incoming arinc 429 data to be stored in the corresponding receive chan- nel fifo (as well as the rx ram) when the data match condi- tions are met. bits 14 and 15 of each dmt entry provide the ability to cause one of three general purpose interrupts upon a data match con- dition. if set to ?00? then no interrupt will occur upon a data match condition (more information on interrupts is described later). arinc 429 transmitter(s) the dd-42900 supports two arinc 429 transmitters. each of these channels transmits data independently and are designat- ed tx0 and tx1. the transmit output of the dd-42900 is a ttl encoded digital data stream which can be connected directly to ddc?s dd-03182 arinc 429 line driver. transmit data rates can be programmed for channels 0 and 1 independently. the transmit data rate is determined by the high- speed/low-speed bit for each of the tx channels in arinc control register 1 and the associated arinc clock input (arinc clk 0 or arinc clk 1). the two, 1 mhz arinc clock inputs may be tied to the 1 mhz clock output or may be con- nected to another clock source to achieve transmit data rates other than 100 khz or 12.5 khz. the transmit clock input should be 10 times (for high-speed mode) or 80 times (for low-speed mode) the desired arinc transmit data rate. transmit fifos: each transmitter channel is provided with an output fifo which is 32 words deep by 32 bits wide. when writ- ing data to the tx fifo, the associated disable txn bit in arinc control register 2 can be set to a logic zero until the fifo is loaded with the desired data. upon setting the disable txn low the transmit channel will send the 32-bit message words with appropriate interword gaps on the arinc 429 output. a status bit indicating that the fifo is empty is supplied for each trans- mitter in the arinc status register. wraparound testing can be performed from tx0 to rx0 and rx1 and from tx1 to rx2 and rx3. wraparound testing is enabled by setting the appropriate bits in arinc control register 1. the parity of the transmitted word can be altered to even parity (instead of the usual odd parity) by setting the associated txn parity bit in the arinc control register 1. this is useful to veri- fy proper operation of the parity check circuitry for each of the receive circuits during wraparound test mode.
4 data device corporation www.ddc-web.com dd-42900 figure 2. dd-00429fp asic mechanical outline (plastic) 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 pin no. 1 index 1 160 120 121 81 80 41 40 pin numbers for ref. only 0.0256 (.65) (typ) 0.133 (3.38) (ref) 0.077(1.96) (typ) 1.256 0.01 (31.9) (typ) see detail "a" detail "a" nts 0.016 (0.41) (min) (typ) 0.031(.79) (typ) 0.007 0.002 (0.18) (typ) 0.146 +0.008 (3.71) -0.000 0.013 +0.000 (0.33) -0.003 0.012 0.003 (0.3 0.08 ) (typ) 1.102 0.004 (27.99 0.1 ) 1.102 0.004 (27.99 0.1 ) notes: 1 lead cluster to be centralized about case centerline within 0.010 (0.25). 2. dimensions in inches (millimeters). processor interface the processor interface allows for the use of either an 8- or 16- bit data bus. intel or motorola control signal formats can also be used. interrupt operational modes the dd-42900 provides four interrupt outputs. three of these interrupt outputs (irq1, irq2, and irq3) are general purpose programmable interrupts. the fourth interrupt is an error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable. error interrupt operation when an error condition occurs, the err or output pin goes low to indicate the presence of an error. the error pin will go high again when the error status register is clear. each of these bits is cleared by either reading the error status register or remov- ing the error condition. general purpose interrupts the three general purpose interrupt outputs can be used for mul- tilevel interrupts or to trigger other external hardware for various conditions. each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to irq0 which does not exist). each interrupt output can be pro- grammed to be either a level interrupt or pulse interrupt via irq control register 2. when programmed for pulse interrupt mode, the associated interrupt pin will go low for 1 s and return high again. when programmed for level interrupt mode, the interrupt will remain until the associated irq status register is read, thus clearing the associated bits in each interrupt register. each of the individual interrupt registers can be masked by set- ting their corresponding bit in irq control register 1. it should be noted that the masking function only prevents the associated irq pin from becoming active. when the mask bit is cleared, an interrupt can occur in level irq mode if one or more interrupt conditions occurred during the time when the mask was set. if the user needs to ensure the interrupt will not occur upon clear- ing the mask bit, the cpu should be programmed to read the associated interrupt status register immediately prior to clearing the irq mask bit. zero wait mode operation: when zero wait mode is enabled by not grounding the zero wait pin, the host microprocessor may read data from the dd-42900 shared memory resources (dmt and rx ram) without using the ready or dtack signals to insert wait states into the microprocessor cycle. this is accom- plished by an additional ? dummy read ? of the desired address. this dummy read causes the dd-42900 to fetch the data from the source and place it in a latch. the data can then be read from the latch (word-by-word or byte-by-byte) by reading the same addresses. thus for a 32-bit read in 8-bit mode, the micro- processor would perform a total of five read operations. the first read would be the dummy read; subsequent reads would trans- fer the data. *indicates an active low
5 data device corporation www.ddc-web.com dd-42900 figure 3b. dd-42900fp flat pack mechanical assembly .010 2.400 0.550 24 25 32 33 0.185 .010 envelope component (max) 0.040 (typ) 2.170 .010 0.200 see detail "a" 0.065 (typ) detail "a" (ref) nts (typ) 0.075 0.185 (typ) 0.040 0.015 (typ) (typ) 0.080 (typ) .002 (typ) 0.010 0.020 r max for ref only pin numbers 23 eq. sp. @ (tol non cum) 0.100 = 2.300 1 64 57 0.100 (typ) 0.020 56 .010 (tol non cum) 7 eq. sp. @ .010 0.100=0.700 1.800 (typ) 1 lead cluster to be centralized 1 about pwb centerline within .010 notes: .003 24 25 32 33 0.100=0.700 7 eq. sp. @ (tol non cum) 1.800 2.400 .010 64 1 0.550 .010 (typ) 0.100 57 56 0.020 0.100 = 2.300 (tol non cum) 23 eq. sp. @ .010 for ref only pin numbers (typ) .003 1 see detail "a" detail "a" nts (typ) 0.015 0.070 (typ) 0.080 (typ) (typ) 0.010 0.020 r max (typ) 0.34 (min) .002 0.100 (ref) 2.000 (typ) 0.100 .010 0.040 envelope component .010 0.200 (max) figure 3a. dd-42900dp dip mechanical assembly component side component side
6 data device corporation www.ddc-web.com dd-42900 gnd tx db10 tx db9 160 159 158 gnd bist r2 (n/c) bist r1 (n/c) 120 119 118 gnd bist tob (n/c) bist toa (n/c) 80 79 78 gnd +5v gnd 40 39 38 tx db8 157 bist r0 (n/c) 117 +5v 77 bist r3 (n/c) 37 tx db7 156 arinc clk 0 116 master reset 76 cs2 36 tx db6 155 arinc clk 1 115 err or 75 cs1 35 tx db5 154 arinc clk out 114 dt a ck 74 cs0 34 tx db4 153 reset rc 113 wr or rd/wr 73 a10 33 tx db3 152 irq1 112 rd or ds 72 a9 32 tx db2 151 irq2 111 ready 71 a8 31 tx db1 150 irq3 110 zero wait mode 70 a7 30 tx db0 149 gnd 109 tmb7 (n/c) 69 a6 29 gnd 148 gnd 108 tmb6 (n/c) 68 a5 28 ld tx0 lo 147 d15 107 tmb5 (n/c) 67 a4 27 lo ad tx0 hi 146 d14 106 tmb4 (n/c) 66 a3 26 tx0 empty 145 d13 105 tmb3 (n/c) 65 a2 25 tx0a in 144 d12 104 tmb2 (n/c) 64 a1 24 tx0b in 143 d11 103 tmb1 (n/c) 63 a0 23 en tx0 out 142 d10 102 tmb0 (n/c) 62 gnd 22 cw strb0 141 d9 101 gnd 61 tx1 b 21 reset 0 140 d8 100 +5v 60 tx1 a 20 gnd 139 +5v 99 tsb1 (n/c) 59 tx0 b 19 +5v 138 gnd 98 tsb0 (n/c) 58 tx0 a 18 rx rd y 2 137 +5v 97 tma7 (n/c) 57 +5v 17 rx rd y 3 136 gnd 96 tma6 (n/c) 56 8/16 bit 16 en rx2 135 d7 95 tma5 (n/c) 55 intel/mo t o 15 en rx3 134 d6 94 tma4 (n/c) 54 gnd 14 16 mhz clock 133 d5 93 tma3 (n/c) 53 gnd 13 +5v 132 d4 92 tma2 (n/c) 52 gnd 12 gnd 131 d3 91 tma1 (n/c) 51 rx rd y0 11 +5v 130 d2 90 tma0 (n/c) 50 rx rd y1 10 ld tx1 lo 129 d1 89 tsa3 (n/c) 49 select 9 ld tx1 h i 128 d0 88 tsa2 (n/c) 48 en rx0 8 tx1 empty 127 bist ram24 (n/c) 87 tsa1 (n/c) 47 en rx1 7 tx1 a in 126 bist ram7 (n/c) 86 tsa0 (n/c) 46 tx db15 6 tx1 b in 125 bist dmt (n/c) 85 tsb3 (n/c) 45 tx db14 5 en tx1 out 124 bist t1b (n/c) 84 tsb2 (n/c) 44 tx db13 4 cw strb1 123 bist t1a (n/c) 83 gnd 43 tx db12 3 reset 1 122 osc clk out (n/c) 82 xtal1 (n/c) 42 tx db11 2 +5v 121 +5v 81 +5v 41 +5v 1 description pin no . descriptio n p in no. description pin no. description pin no. table 4. dd-00429fp asic pinouts table 3. dd-42900 pinouts (dip and flat pack) pin no. 1 function gnd pin no. 17 function a8 pin no. 33 function d0 pin no. 49 function irq3 2 gnd 18 a9 34 d1 50 irq2 3 intel/mo t o 19 a10 35 d2 51 irq1 4 8/16 bit 20 cs0 36 d3 52 1 mhz out 5 tx0 a 21 cs1 37 d4 53 arinc clk 1 6 tx0 b 22 cs2 38 d5 54 arinc clk 0 7 tx1 a 23 gnd 39 d6 55 +5v 8 tx1 b 24 gnd 40 d7 56 +5v 9 a0 25 zero wait mode 41 d8 57 rx3 b 10 a1 26 ready 42 d9 58 rx3 a 11 a2 27 rd (ds ) 43 d10 59 rx2 b 12 a3 28 wr (rd/wr ) 44 d11 60 rx2 a 13 a4 29 dt a ck 45 d12 61 rx1 b 14 a5 30 err or 46 d13 62 rx1 a 15 a6 31 master reset 47 d14 63 rx0 b 16 a7 32 16 mhz clock 48 d15 64 rx0 a
7 data device corporation www.ddc-web.com dd-42900 ordering information full assembly: dd-42900xp - 200 burn-in: 0 = no burn-in temperature range: 2 = -40 - +85 c asic package type: p = plastic lead type: d = dip f = flat pack chip set: dd-00429xp - x00 temperature range: 2 = -40 - +85 c 9 = -55 - +85 c (fp package only) asic package type: p = plastic lead type: f = 160-pin quad flat pack v = 144-pin tqfp note: the dd-03182 and dd-03282 are required to complete the arinc 429 interface. the dd-00429 is the microprocessor interface/ram/fifo and interrupt controller. application note an/a-6 dd-42900 frequently asked questions is available on request. note: these transceiver/line driver part numbers are provided for historical reference only. these components are now provid- ed by device engineering inc. for a complete cross-reference chart, please visit dei at www.deiaz.com, (480) 303-0822.
8 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. c1-02/01-0 printed in the u.s.a. data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7435 headquarters - tel: (631) 567-5600 ext. 7435, fax: (631) 567-7358 west coast - tel: (714) 895-9777, fax: (714) 895-4988 southeast - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com
|
